PRODUCT INNOVATIONS
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Mixed signal software design tool supports automotive version of power manager devices
Lattice Semiconductor announced the release of its PAC-Designer
software design tool suite, version 4.99a. The tool suite now supports
Lattice’s AECQ100-qualified automotive Power Manager II
(LA-ispPAC-POWR1014/A) devices. The PAC-Designer tool suite also
provides easy to use, point-and-click, intuitive design and
verification support for all Power Manager and ispClock™ mixed
signal devices.
“Today’s automotive designs use advanced CPUs, FPGAs and ASICs, which increases the number of board-mounted power supplies,” said Stan Kopec, Lattice corporate vice president of marketing. “Using Lattice’s PAC-Designer software tools, designers can quickly implement and fine tune the power management algorithm used to control and monitor these diverse power supplies. The resulting board-specific power management design is more accurate, requires less circuit board area and costs less than traditional designs using multiple off-the-shelf dedicated devices.”
Common power management functions found on circuit boards include hot-swap control, voltage supervision, supply sequencing and reset generation. To ensure board reliability, all board-mounted power supplies should be sequenced and monitored via a power management algorithm. Typically, the power management algorithm is either changed or fine tuned during the board debug process to meet unforeseen device power-up behavior. Traditional solutions are hard-wired and cannot be changed without an expensive board re-spin. Lattice’s Windows-based PAC-Designer software enables implementation of a new power management algorithm in Lattice’s Power Manager II devices within minutes.
Similarly, clock network designs require timing adjustments during the board debug phase. The Lattice ispClock devices support an in-system programmable skew mechanism. Using the PAC-Designer software, designers can precisely alter the clock skew of each of the clock nets. Traditionally, clock skew has been implemented by “snaking” clock traces on the board, and any change to the skew was implemented through a time consuming, expensive board re-spin. Using the PAC-Designer software, the clock network skew is altered simply by reprogramming the ispClock device.
“Today’s automotive designs use advanced CPUs, FPGAs and ASICs, which increases the number of board-mounted power supplies,” said Stan Kopec, Lattice corporate vice president of marketing. “Using Lattice’s PAC-Designer software tools, designers can quickly implement and fine tune the power management algorithm used to control and monitor these diverse power supplies. The resulting board-specific power management design is more accurate, requires less circuit board area and costs less than traditional designs using multiple off-the-shelf dedicated devices.”
Common power management functions found on circuit boards include hot-swap control, voltage supervision, supply sequencing and reset generation. To ensure board reliability, all board-mounted power supplies should be sequenced and monitored via a power management algorithm. Typically, the power management algorithm is either changed or fine tuned during the board debug process to meet unforeseen device power-up behavior. Traditional solutions are hard-wired and cannot be changed without an expensive board re-spin. Lattice’s Windows-based PAC-Designer software enables implementation of a new power management algorithm in Lattice’s Power Manager II devices within minutes.
Similarly, clock network designs require timing adjustments during the board debug phase. The Lattice ispClock devices support an in-system programmable skew mechanism. Using the PAC-Designer software, designers can precisely alter the clock skew of each of the clock nets. Traditionally, clock skew has been implemented by “snaking” clock traces on the board, and any change to the skew was implemented through a time consuming, expensive board re-spin. Using the PAC-Designer software, the clock network skew is altered simply by reprogramming the ispClock device.
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