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News - 16.10.2008
IMEC demonstrates 3D stacked integrated circuits
IMEC announced that it has made significant progress with its 3D-SIC (3D stacked IC) technology. IMEC recently demonstrated the first functional 3D integrated circuits obtained by die-to-die stacking using 5µm Cu through-silicon vias (TSV). It will now further develop 3D SIC chips on 200mm and 300mm wafers, integrating test circuits from partners participating in its 3D integration research program.
Worldwide semiconductor capital equipment spending to decline 26 Percent in 2008
A collapse in memory spending, combined with a weak economy, is driving a major contraction in semiconductor capital equipment spending in 2008, according to Gartner, Inc. The slowdown is expected to continue into 2009 before the industry recovers in 2010.
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